使用现有测试设备和平台实现串行RapidIO协议分析
Design validation of parallel buses is challenging but fairly straight forward. Parallel busses by nature are made up of an address bus, a data bus (sometimes multiplexed), control signals and a clock. More sophisticated high speed parallel buses may even contain several clocks, thus creating multiple time domains. The tools that engineers use to validate these busses are available and are a fairly close match, architecturally, to the task of attaching and decoding parallel busses. These tools are generally scopes and logic analyzers.
In many cases, specialized hardware and software for parallel bus analysis are available that attach to and run on the scope or logic analyzer to help with protocol decode and timing analysis. However, even in the absence of these specialized add on’s, engineers could observe parallel buses with just high speed sampling. Armed with a timing diagram and the general output of the logic analyzer or scope engineers can still get a rough idea of what was going on.
Serial interconnects are different. Since the data is encoded and involves clock recovery, simple high speed data sampling reveals only eye diagrams (Figure 1). These serial interconnects such as Serial RapidIO are replacing parallel buses in today’s systems; however, the function that these interconnects provide remains largely the same: they move data quickly and efficiently from one functional area to another. For design validation and debug, engineers still have the same issues including:
- checking for general system integrity,
- looking for protocol errors to ensure specification compliance,
- finding events that lead up to a system hang or lockup, and
- measuring performance through devices.
With the advent of serial interconnects changing the overall computer architecture landscape what will engineers do with their general purpose parallel bus oriented test equipment?
Figure 1 Eye diagram of a serial interconnect contrasted with a parallel bus as viewed from a logic analyzer
The digital oscilloscope with its low channel count and high speed sampling can still be used for serial interconnect debug in that it can show compliance to the specification eye diagrams. By its very nature the oscilloscope can make the transition from parallel bus debug tool to serial interconnect debug tool, but what about the logic analyzer? The logic analyzer sampling time is not fast enough and for protocol state analysis there is no separate signal that can be used as the clock. For serial interconnects protocol analysis engineers now have to choose between a new dedicated serial interconnect oriented tool, or a new innovative add on to their existing logic analyzer.
General purpose logic analyzer versus dedicated protocol analyzer
